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features ? ballast control and half-bridge driver in one ic ? transformer-less lamp power sensing ? closed-loop lamp power control ? closed-loop preheat current control ? programmable preheat time ? programmable preheat current ? lamp ignition detection ? programmable ignition-to-dim time ? 0.5 to 5vdc dimming control input ? min and max lamp power adjustments ? programmable minimum frequency ? internal current sense blanking data sheet no. pd60194 revd dimming ballast control ic typical connection description description: the ir21592/ir21593 are complete dimming ballast controllers and 600v half-bridge drivers all in one ic. the architecture includes phase control for trans- former-less lamp power sensing and regulation which minimizes changes needed to adapt non-dimming ballasts for dimming. externally programmable features such as preheat time and current, ignition-to-dim time, and a complete dimming interface with minimum and maximum settings provide a high degree of flexibility for the ballast design engineer. protection from failure of a lamp to strike, filament failures, thermal overload, or lamp failure during normal operation, as well as an automatic restart function, have been included in the design. the heart of this control ic is a voltage- controlled oscillator with externally programmable minimum frequency. the ir21592/ ir21593 are available in both 16 pin dip and 16 pin narrow body soic packages. 16 15 14 13 4 3 2 1 5 6 7 11 10 8 9 12 vdc vco iph fmin min max dim cph cs lo com vcc vb vs ho sd + dc bus + rectified ac line - dc bus r min c ph c vco r cs r max r fmin r iph 0.5 to 5vdc r dim c vdc r vdc r vac r pull-up single lamp dimmable packages 16 lead soic (narrow body) www.irf.com 1 ir21592 ( s ) & ( pbf ) ir21593 ( s ) & ( pbf ) ? full lamp fault protection ? brown-out protection ? automatic restart ? micro-power startup ? zener clamped vcc ? over-temperature protection ? 16-pin dip and soic package types 16 lead pdip

ir21592/ir21593 ( s ) & ( pbf ) 2 www.irf.com absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com, all currents are defined positive into any lead. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. symbol definition min. max. units v b high side floating supply voltage -0.3 625 v s high side floating supply offset voltage v b - 25 v b + 25 v ho high side floating output voltage v s - 0.3 v b + 0.3 v lo low side output voltage -0.3 v cc + 0.3 i omax maximum allowable output current (either output) -500 500 due to external power transistor miller effect v vco voltage controlled oscillator input voltage -0.3 6.0 v i cph cph current -5 5 ma v iph iph voltage -0.3 5.5 v dim dimming control pin input voltage -0.3 5.5 v max maximum lamp power setting pin input voltage -0.3 5.5 v min minimum lamp power setting pin input voltage -0.3 5.5 v cs current sense input voltage -0.3 5.5 i sd shutdown pin current -5 5 i cc supply current (note 1) 25 dv/dt allowable offset voltage slew rate -50 50 v/ns p d package power dissipation @ t a +25 c (16 pin dip) 1.60 p d = (t jmax -t a )/rth ja (16 pin soic) 1.25 rth ja thermal resistance, junction to ambient (16 pin dip) 75 (16 pin soic) 115 t j junction temperature -55 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) 300 v ma v ma note 1: this ic contains a zener clamp structure between the chip v cc and com which has a nominal breakdown voltage of 15.6v (v clamp ). please note that this supply pin should not be driven by a dc, low impedance power source greater than the diode clamp voltage (v clamp ) as specified in the electrical characteristics section. w o c o c/w
ir21592/ir21593 ( s ) & ( pbf ) www.irf.com 3 note 2: enough current should be supplied into the vcc lead to keep the internal 15.6v zener clamp diode on this lead regulating its voltage, v clamp . note 3: the max lead is a voltage-controlled current source. for optimum dim interface current mirror performance, this current should be kept between 0 and 750 a. recommended operating conditions for proper operation the device should be used within the recommended conditions. symbol definition min. max. units v bs high side floating supply voltage v cc - 0.7 v clamp v s steady state high side floating supply offset voltage -1 600 v cc supply voltage v ccuv+ v clamp (15.6) i cc supply current note 2 10 ma v vco vco pin voltage 05 v dim dim pin voltage 0.5 5.0 v max max pin current (note 3) -750 0 a v min min pin voltage 1 3 v bsmin minimum required v bs voltage for proper ho functionality 5 r fmin minimum frequency setting resistance 10 100 k ? i sd shutdown pin current -1 1 i cs current sensing pin current -1 1 t j junction temperature -40 125 o c v v ma electrical characteristics v cc = v bs = v bias = 14v +/- 0.25v, v cs = 0.5v, v sd = 0.0v, r fmin = 40k, c vco = 10 nf, v dim = 0.0v, r max = 33k, r min = 56k, v cph = 0.0v, c lo,ho = 1000pf, t a = 25 o c unless otherwise specified. supply characteristics v ccuv+ v cc supply undervoltage positive going 12.0 12.5 13.0 threshold v cchys v cc supply undervoltage l ockout hysteresis 1.5 1.6 1.7 i qccuv uvlo mode quiescent current 70 200 330 v cc = 10v i qccflt fault-mode quiescent current 240 sd=5v, cs=2v, or tj > t sd i ccfmin v cc supply current @ fmin (ir21592) 5.6 v vco = 0v i ccfmax v cc supply current @ fmax (ir21592) 6.0 v vco = 5v i ccfmin v cc supply current @ fmin (ir21593) 5.4 v vco = 0v i ccfmax v cc supply current @ fmax (ir21593) 6.8 v vco = 5v v clamp v cc zener shunt clamp voltage 14.5 15.6 16.5 v i cc = 10ma symbol definition min. typ. max. units test conditions a v ma v
ir21592/ir21593 ( s ) & ( pbf ) 4 www.irf.com electrical characteristics (cont.) v cc = v bs = v bias = 14v +/- 0.25v, v cs = 0.5v, v sd = 0.0v, r fmin = 40k, c vco = 10 nf, v dim = 0.0v, r max = 33k, r min = 56k, v tph = 0.0v, c lo,ho = 1000pf, t a = 25 o c unless otherwise specified. symbol definition min. typ. max. units test conditions floating supply characteristics i bsfmin v bs supply current (low freq.) 0 v vco = 0v i bsfmax v bs supply current (high freq.) 30 v vco = 5v i lk offset supply leakage current 50 v b = v s = 600v a oscillator i/o characteristics f vco vco frequency range (ir21592) 16.5 18 26 v vco =0v, rfmin=40k ? (see graph 11) 73 95 108 v vco =5v, rfmin=40k ? f vco vco frequency range (ir21593) 30 v vco =0v, rfmin=40k ? (see graph 12) 230 v vco =5v, rfmin=40k ? d gate drive outputs duty cycle 50 % v vco = 2.5v v vcoflt fault-mode vco pin voltage (uvlo, 5 v shutdown, over-current/temp.) i vcoph preheat mode vco pin discharge current 1.0 v cph =2.5v, v iph =0.5v i vcodim dim mode vco pin discharge current 16.0 v vco =2.5v, v cph =5.5v, v iph =0.5v, 1v pulse at cs a khz tr turn-on rise time 48.5 120 180 tf turn-off fall time 24.25 65 145 gate driver output characteristics ns i vcopk amplitude control vco pin charging current 60 a v cph =0v, v cs =1v, v iph =0.5v, v vco =2.5v t dtlo lo output deadtime (ir21592) 1.8 t dtho ho output deadtime (ir21592) 1.8 t dtlo lo output deadtime (ir21593) 1.0 t dtho ho output deadtime (ir21593) 1.0 s v vco =0v, v min =1.5v, v iph =0.5v
ir21592/ir21593 ( s ) & ( pbf ) www.irf.com 5 electrical characteristics (cont.) v cc = v bs = v bias = 14v +/- 0.25v, v cs = 0.5v, v sd = 0.0v, r fmin = 40k, c vco = 10 nf, v dim = 0.0v, r max = 33k, r min = 56k, v tph = 0.0v, c lo,ho = 1000pf, t a = 25 o c unless otherwise specified. symbol definition min. typ. max. units test conditions v fmin fmin pin voltage during normal operation 4.6 5.1 6.25 v vmin=1.5v,viph=0.5v v fminflt fmin pin voltage during fault mode 0.0 v sd = 5v, or cs = 2v, or tj > tsd minimum frequency setting v sdth+ rising shutdown pin threshold voltage 1.6 2.0 2.6 vcph =viph=0v v csth peak over current threshold 1.2 1.6 1.9 vcph < 5v v vdcth+ rising vdc pin threshold voltage 5.1 vcph=vcs=vsd=0v v sdhys sd threshold hysteresis 150 mv v cph =viph=0v v vdchys vdc threshold hysteresis 2.1 vcph=vcs=vsd=0v v sdclmp sd pin clamp voltage 7.6 isd = 100ma t sd thermal shutdown junction temperature 165 o c protection characteristics v v v csthzx zero-crossing threshold voltage 0.0 v v cph =5.5v,viph=0.5v t blank zero-crossing internal blank time 291 400 1030 ns v cph =5.5v,viph=0.5v phase control v dimoff dim pin offset voltage 0.5 v minmin dim minimum reference voltage (min pin) 1.0 v cph =5.5v,viph=0.5v v minmax dim maximum reference voltage (min pin) 3.0 v cph =0.5v,viph=0.5v dimming interface v preheat characteristics i cph cph pin charging current 0.8 1.3 2.1 a vcph=vdim=4.7v, vcs=1.0v v cphign cph pin ignition mode threshold voltage 4.3 5.0 5.7 vcs=2.0v v cphclmp cph pin clamp voltage 10 vcs=vdim=viph=0v i iph iph pin dc source current 25 a vcph=vdim=4.7v, iiph=1/rfmin v csthph peak preheat current regulation threshold 0.7 v riph=27k, vmin=0v, vcph=0v, vcsth = (iiph) x (riph) v cphflt cph pin voltage during uvlo or fault 0.0 v sd = 5v, or cs = 2v, or tj > tsd v ignition detection i iphign+ iph source current (vcs rising) 30 vcs=0v, riph=18k, vcph>5.1v i iphign- iph source current (vcs falling) 27.5 vcs =1.0v, vcph>5.1v a
ir21592/ir21593 ( s ) & ( pbf ) 6 www.irf.com lead assignments & definitions block diagram pin # symbol description 1 11 10 9 3 8 7 6 5 4 2 16 15 14 13 12 vdc ho vb vs vcc com lo cs sd fmin min max dim cph vco line input voltage detection voltage controlled oscillator input preheat timing input 0.5 to 5vdc dimming control input maximum lamp power setting minimum lamp power setting minimum frequency setting shutdown input current sensing input low-side gate driver output ic power & signal ground logic & low-side gate driver supply high-side gate driver floating supply high voltage floating return high-side gate driver output pin assignments 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vdc vco cph dim max min fmin iph lo com vcc vb vs ho sd cs iph peak preheat current reference level shift pulse filter & latch 3 5.1v 4 6 10v 2 1.0ua 5 7 8 5.1v 1.0v cph dim max min fmin iph vco q s r2 q r1 q t rq 16 14 15 vs ho vb 13 11 12 com lo vcc 15.6v 10 1.6v cs under- voltage detect 1 vdc i ct i ct 15ua 1ua 60ua ct i fmin q s rq q s rq i dim 5.1v 1 0 vcc 400ns delay 5.1v 3v r fb v err ref fb ct over- temp detect ign det qs r q 9 sd 2.0v 7.6v q s rq i dt i ct + i dim /5 4/r fmin 1/r fmin 0.1/r fmin 0.1/r fmin
ir21592/ir21593 ( s ) & ( pbf ) www.irf.com 7 state diagram preheat mode 1/2-bridgeoscillator on v cspk +v iph (peak current control) cph charging@i ph +1 a dim+open circuit over-current disabled uvlo mode 1/2-bridge off iqcc=200ma cph=0v oscillator off fault mode fault latch set 1/2-bridge off i qcc =240 a cph=0v vcc=15.6v oscillator off dim mode phase cs =phase ref dim=cph over-current enabled cph > 5.1v (end of preheat mode) vcc < 10.9v (vcc fault or power down) or vdc < 3.0v (dc bus/ac line fault or power down) or sd > 2.0v (lamp fault or lamp removal) sd > 2.0v (lamp removal) or vcc < 10.9v (power turned off) cs > v csth (1.6v) (failure to strike lamp or hard switching) or t j > 165c (over-temperature) t j > 165c (over-temperature) cs > v csth (1.6v) (over-current or hard switching) or t j > 165c (over-temperature) v cs >v iph (enable ignition detection) then v cs 12.5v (uv+) and vdc > 5.1v (bus ok) and sd < 1.7v (lamp ok) and t j < 165c (t jmax ) power turned on ignition mode f ph ramps to fmin cph charging@i ph +1 a dim=open circuit over-current enabled
ir21592/ir21593 ( s ) & ( pbf ) 8 www.irf.com vdc cph vco sd ho lo ph flt ign sd ph ign dim uvlo uvlo vdcth- vdcth+ 5.1v v dim 5v 5v cs 1.6v v iph vcc uvlo- uvlo+ 15.6v f timing diagram non-strike fault condition with lamp exchange
ir21592/ir21593 ( s ) & ( pbf ) www.irf.com 9 external components selection procedure (note: please refer to "typical connection" diagram, page 1) calculate r cs pk ign cs i r 6 . 1 = r cs sets the maximum ignition current which corresponds to the maximum ignition voltage across the lamp. r cs i ign v ign select r fmin use graph 1 or graph 2 the minimum operating frequency must be lower than f 100% of f ign (whichever is lower). r fmin also programs i min and i iph , so r fmin must be set first. r fmin f min begin calculate r pull-up qccuv on turn up pull i vac r ? ? = set r vac and r vdc such that the voltage on pin vdc will exceed 5.1 volts at the desired line turn-on voltage. r vdc vac turn-on calculate r vdc o n tur n va c o n tur n vd c vac r vac r ? ? ? ? ? ? ? ? ? ? ? = 1 . 5 1 1 . 5 the voltage at pin iph is the reference for amplitude current control during preheat mode. r iph must be set after r fmin . r iph i ph v ph select & calculate r iph use graph 8 to find i iph , then calculate r iph : ip h c s p h ip h i r i r pk ? = calculate c cph () ph cph t e c 7 6 . 2 ? = during preheat, an internal 1.3 a current source at pin cph charges external capacitor ccph. preheat mode ends when vcph exceeds 5.1 volts. c cph t ph calculate ? min (equations 8 & 9) r min sets the lower phase boundary corresponding to minimum lamp power when v dim = 0 volts. r min must be set after r fmin . r min ? min p lamp calculate r max use equation 15 r max ? max p lamp r max sets the upper phase boundary corresponding to maximum lamp power when v dim = 5 volts. r max must be set after r fmin and r min . find v min (graph 9) find i min (graph 3) min min min i v r = calculate r min
ir21592/ir21593 ( s ) & ( pbf ) 10 www.irf.com graph 3. i min vs r fmin (ir21592/ir21593) graph 4. i iph vs r fmin (ir21592/ir21593) characteristic curves graph 2. frequency vs r fmin (ir21593) graph 1. frequency vs r fmin (ir21592) 0 20 40 60 80 100 120 10 20 30 40 50 60 70 rfmin ( k ? ) frequency (khz) v vco =5v v vco =2v v vco =0v 0 40 80 120 160 200 10 20 30 40 50 60 70 rfmin ( k ? ) frequency (khz) v vco =5v v vco =2v v vco =0v 50 100 150 200 250 300 350 400 450 10 20 30 40 50 60 70 r fmin (k ? ) i min ( a) 10 20 30 40 50 60 70 80 90 100 110 10 20 30 40 50 60 70 r fmin (k ? ) i iph ( a)
ir21592/ir21593 ( s ) & ( pbf ) www.irf.com 11 graph 5. ? ii vs /v vs i vs v min (ir21592/ir21593) -90 -75 -60 -45 -30 -15 0 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 v mi n (v) ii vs i/v vs i graph 6. r min vs v min 0 0.5 1 1.5 2 2.5 3 -25 0 25 50 75 100 125 temperature c i cph a graph 7. i cph vs temperature (ir21592/ir21593) graph 8. i min vs temperature (ir21592/ir21593) 5 10 15 20 25 30 2 2.2 2.4 2.6 2.8 3 v mi n (v) r f m in = 3 9 k r f m in = 1 0 k r f m in = 1 6 k rfmin=20k rfmin=33k rfmin=27k r min (k ? ) 90 100 110 120 130 140 150 -25 0 25 50 75 100 125 temperature c i min a
ir21592/ir21593 ( s ) & ( pbf ) 12 www.irf.com graph 10. v fmin vs temperature (ir21592/ir21593) graph 9. i ph vs temperature (ir21592/ir21593) graph 12. frequency vs temperature (ir21593) rfmin=39k graph 11. frequency vs temperature (ir21592) rfmin=39k 0 20 40 60 80 100 -25 0 25 50 75 100 125 temperature c frequency (khz) v vco =3v v vco =5v v vco =0v 0 40 80 120 160 -25 0 25 50 75 100 125 temperature c frequency (khz) v vco =3v v vco =5v v vco =0v 20 24 28 32 36 40 -25 0 25 50 75 100 125 temperature c i iph a 4 4.4 4.8 5.2 5.6 6 -25 0 25 50 75 100 125 temperature c v fmin (v)
ir21592/ir21593 ( s ) & ( pbf ) www.irf.com 13 20 24 28 32 36 40 -25 0 25 50 75 100 125 temperature c 4 4.4 4.8 5.2 5.6 6 -25 0 25 50 75 100 125 temperature c v fmin (v) graph 13. i iph vs temperature (ir21592/ ir21593) graph 14. v fmin vs temperature (ir21592/ ir21593) i iph ( a) 1 1.4 1.8 2.2 2.6 3 -25 0 25 50 75 100 125 temperature c t dead (us) 0 0.4 0.8 1.2 1.6 2 -25 0 25 50 75 100 125 temperature c t dead (us) graph 15. tdead vs temperature (ir21592) graph 16. tdead vs temperature (ir21593)
ir21592/ir21593 ( s ) & ( pbf ) 14 www.irf.com functional description phase control to understand phase control, a simplified model for the ballast output stage is used (figure 1). the lamp and filaments are replaced with resistors, with the lamp inserted between the filament resistors (r1, r2, r3 and r4). l c rlamp vin r1 r2 r3 r4 figure 1, dimming ballast output stage. during preheat and ignition (figure 2), the circuit is a high-q series lc with a strong input current to input voltage phase inversion from +90 to -90 degrees at the resonance frequency. for operating frequencies slightly above resonance and higher, the phase is fixed at -90 degrees for the duration of preheat and ignition. during dimming, the circuit is an l in series with a parallel r and c, with a weak phase inversion at high lamp power and a strong phase inversion at low lamp power. -30 -20 -10 0 10 20 5 101520253035404550 frequency [khz] magnitude [db] -100 -50 0 50 100 150 200 250 300 350 400 phase [deg] 10% 50% 100% 100% 50% 10% ph/ign ph/ign figure 2, typical output stage transfer function for different lamp power levels. in the time domain (figure 3), the input current is shifted -90 degrees from the input half-bridge voltage during preheat and ignition, and somewhere between 0 and -90 degrees after ignition during running. zero phase-shift corresponds to maximum power. n run v in i in t ph/ign 0 i in run n ph/ign figure 3, typical ballast output stage waveforms. when the phase is calculated and plotted versus lamp power (figure 4), the result is a linear dimming curve, even down to ultra-low light levels where the resistance of the lamp can change by orders of magnitude.
ir21592/ir21593 ( s ) & ( pbf ) www.irf.com 15 -90.0 -85.0 -80.0 -75.0 -70.0 -65.0 -60.0 0 5 10 15 20 25 30 lamp power [watts] phase [degrees] figure 4, lamp power vs. phase of output stage. under-voltage lock-out (uvlo) the ir21592/ir21593 undervoltage lock-out is designed to maintain an ultra low quiescent current of less than 200ua, while guaranteeing the ic is fully functional before the high and low side output drivers are activated. figure 5 shows an efficient supply voltage using the start-up current of the ir21592/ir21593 together with a charge pump from the ballast output stage (r1, c1, c2, d1 and d2). 16 15 14 13 12 11 lo com vcc vb vs ho rectified ac line half-bridge output c1 r1 d1 d2 q2 q1 rvdc c2 v bus (+) d3 c3 rcs v bus (-) 1 vdc r3 cvdc discharge time internal clamp voltage vhyst v uvlo+ v uvlo- charge pump output t v c1 r1 & c1 time constant c1 discharge figure 6, start-up capacitor (c1) voltage. during the discharge cycle, the rectified current from the charge pump charges the capacitor above the minimum operating voltage of the device and the charge pump and internal 15.6v zener clamp of the ic take over as the supply voltage. the start-up capacitor and snubber capacitor must be selected such that worst case ic conditions are satisfied. a bootstrap diode (d3) and supply capacitor (c3) comprise the supply voltage for the high side driver circuitry. to guarantee that the high-side supply is charged up before the first pulse on pin ho, the first pulse from the output drivers comes from the lo pin. during uvlo, the high and low side driver outputs are low, pin vco is pulled-up internally to 5v resetting the starting frequency to the maximum, and pin cph is short-circuited internally to com resetting the preheat time. figure 5, typical application of start-up circuitry. the start-up capacitor (c1) is charged by current through resistor (r1) minus the start-up current drawn by the ic. this resistor is typically chosen to provide 2x the maximum start-up current at low line to guarantee start-up under the worst case condition. once the capacitor voltage reaches the start-up threshold, and, the voltage on pin vdc is above 5.1v (see brown-out protection), the ic turns on and ho and lo begin to oscillate. the capacitor begins to discharge due to the increase in ic operating current (figure 6).
ir21592/ir21593 ( s ) & ( pbf ) 16 www.irf.com brown-out protection in addition to the voltage on vcc being above the start-up threshold, pin vdc must also be above 5.1v for ho and lo to begin oscillating. a voltage divider (r3,rvdc) from the rectified ac line connected to pin vdc measures the rectified ac line input voltage to the ballast and programs the turn-on and turn-off line voltages. a filter capacitor (cvdc) is also connected to pin vdc that must be chosen such that the ripple is low enough and the lower turn-off threshold of 3v is not crossed during normal line conditions. this detection is necessary due to the possibility of the lamp extinguishing during low-line conditions before the ic is properly reset. should a brown- out occur, the dc bus can drop to a level below the minimum required for the tank circuit to maintain the necessary lamp voltage. this detection will insure a clean turn-off before the dc bus drops too low and properly resets the ic to the preheat mode when the line returns. preheat (ph) the ir21592/ir21593 enters preheat mode when vcc exceeds the uvlo+ threshold and vdc exceeds 5.1v. ho and lo begin to oscillate at the maximum operating frequency with 50% duty cycle and at the internally set dead-time of 2us (ir21592) or 1 s (ir21593). pin cph is disconnected from com and an internal 1ua current source (figure 7) charges the external timing capacitor on cph linearly. 3 7.6v 2 1ua 7 8 cph fmin iph vco 11 12 com lo 10 cs 1ua 60ua i fmin 1/r fmin 5.1v q2 rcs vco ph logic 16 ho q2 15 vs r fmin r iph c cph c vco half bridge output i load v bus (+) v bus (-) load return half bridge driver ir21592/ir21593 figure 7, ir21592/ir21593 preheat circuitry. an internal 1ua current source slowly discharges the external capacitor on pin vco and the voltage on pin vco begins to decrease. this decreases the frequency, which, for operating frequencies above resonance, increases the load current. when the peak voltage measured on pin cs, produced by a portion of the load current flowing through an external sense resistor (rcs), exceeds the voltage level on pin iph, a 60ua internal current source is connected to pin vco and the capacitor charges (figure 8). this forces the frequency to increase and the load current to decrease. when the voltage on pin cs decreases below the voltge on pin iph, the 60ua current source is disconnected and the frequency decreases again.
ir21592/ir21593 ( s ) & ( pbf ) www.irf.com 17 60ua -1ua t t t t v cvco i cvco v rcs vs lo ho v iph figure 8, peak load current regulation timing diagram. this feedback keeps the peak preheat current regulated to the user-programmable setting on pin iph for the duration of the preheat time. an internal current source connected to an external resistor on pin iph sets a voltage reference for the peak pre-heat current. the pre-heat time continues until the voltage on pin cph exceeds 5v. ignition (ign) the ir21592/ir21593 enters ignition mode when the voltage on pin cph exceeds 5v. the peak current regulation reference voltage is disconnected from the user-programmable setting on pin iph and is connected to a higher internal threshold of 1.6v (figure 9). 3 7.6v 2 1ua 4 cph dim vco 11 12 com lo 10 cs 1ua 1.6v q2 rcs vco ph logic 16 ho q2 15 vs r dim c cph c vco half bridge output i load v bus (+) v bus (-) load return half bridge driver ir21592/ir21593 dim interface 0.5 to 5v phase control fault logic figure 9, ir21592/ir21593 ignition circuitry. the ignition ramp is then initiated as the capacitor on pin vco discharges linearly through an internal 1ua current source. the frequency decreases linearly towards the resonance frequency of the high-q ballast output stage, causing the lamp voltage and load current to increase (figure 10). the frequency continues to decrease until the lamp ignites or the current limit of the ir21592/ir21593 is reached. if the current limit is reached, the ir21592/ir21593 enters fault mode. the 1.6v threshold together with the external current sensing resistor on pin cs determine the maximum allowable peak ignition current (and therefore peak ignition voltage) of the ballast output stage. the peak ignition current must not exceed the maximum allowable current ratings of the output stage mosfets or igbts, and, the resonant inductor must not saturate at any time. to prevent a "flash" across the lamp during ignition at low dim settings, an ignition detection
ir21592/ir21593 ( s ) & ( pbf ) 18 www.irf.com circuit measures the voltage at the cs pin and compares it against the voltage at the iph pin. during the rising ignition ramp, the voltage at the iph pin is increased to 20% above its value 5.1v v cph v vco t t ph ign dim v dim r dim & c tph time constant ign-to-dim time figure 10, ir21592/ir21593 ignition detection. during preheat mode. when the voltage on the cs pin exceeds this voltage, the voltage on the iph pin is decreased to viph pre-heat +10% and the ignition detection circuit is then active (see figure 10). when the lamp ignites, the voltage on the cs pin will then fall below the voltage on the iph pin and the ic enters dim mode and the phase control loop is closed. in order for the ignition detection circuit to function properly and for the ic to enter dim mode, the voltage on the cs pin must first rise above viph pre-heat + 20% during the ignition ramp to activate the circuit, and then decrease below viph pre-heat +10% when the lamp ignites. ignition-to-dim (ign-to-dim) when the ir21592/ir21593 enters dim mode, the phase control loop is closed and the phase of the load current is regulated against the user control input on pin dim. to control the rate at which the dim setting changes from maximum brightness to the user setting (ign-to-dim time, figure 11), pin dim is connected internally to pin cph when the ir21592/ir21593 enters dim mode. the resistor on pin dim (rdim) discharges the capacitor on pin cph down to the user dim setting. the resistor can be selected for a fast time constant to minimize the amount of flash visible over the lamp just after ignition, or, a long time constant such that the brightness ramps down smoothly to the user setting. should the ignition-to-dim time be too fast, however, the loop can respond faster than the ionization constant of the lamp (milliseconds) causing the vco to over-shoot. this can result in a frequency that is higher than the minimum brightness frequency and can extinguish the lamp. the capacitor on pin cph serves multiple functions by setting the preheat time, the travel rate just after ignition (together with resistor rdim), and, serving as a filter capacitor on pin figure 11, ir21592/ir21593 ignition timing diagram. v iph v iph + 20% v iph + 10% cs ph ign dim
ir21592/ir21593 ( s ) & ( pbf ) www.irf.com 19 once lock is achieved, the phase detector (pdet) outputs short pulses to an open-drain pmos that charges the vco capacitor through an internal resistor (rfb) each time an error pulse occurs (figure 13). this action "nudges" the integrator at the input of the vco to keep the phase of the output stage current exactly locked in phase with the reference. ref fb v cs t v vco t lo err figure 13, phase control timing diagram. the ir21592/ir21593 includes a dimming interface for analog lamp power control. the dim pin input requires a voltage in the range of 0.5 to 5vdc, with 5v corresponding to minimum phase shift (maximum lamp power). the output of the dim interface is the voltage on pin min, which is compared with the internal timing capacitor (ct) voltage to produce a frequency- independent digital reference phase (figure 14). dim during dimming to increase high-frequency noise immunity and minimize component count. dimming (dim) to regulate lamp power, the error between the reference phase and the phase of the output stage current forces the vco to steer the frequency in the proper direction, as determined by the transfer function of the output stage, such that the error is forced to zero. an internal 15ua current source is connected to pin vco during dimming mode (figure 12) to discharge the vco capacitor and decrease the frequency towards lock. 3 7.6v 2 4 cph dim vco 11 12 com lo 10 cs 16ua 1.6v q2 rcs vco 16 ho q2 15 vs r dim c cph c vco half bridge output i load v bus (+) v bus (-) load return half bridge driver ir2159 dim interface 0.5 to 5v phase control r fb vcc fault logic r max r min 5 6 max min figure 12, ir21592/ir21593 dimming circuitry.
ir21592/ir21593 ( s ) & ( pbf ) 20 www.irf.com 1v 3v 5v 0 0.5v 5v v min v dim r min r max v ct lo user setting dim range 0 -90 -180 ? ref figure 14, dimming interface the charging time of ct from 1v to 5.1v determines the on-time of output gate drivers ho and lo and corresponds to -180 degrees of possible phase shift in load current (minus deadtime). for the 0 to -90 degree dim range, the voltage on pin min is bounded between 1v and 3v using pins min and max. an external resistor on pin max programs the minimum phase shift reference (maximum lamp power) corresponding to 5v on pin dim, and an external resistor on pin min sets the maximum phase shift (minimum lamp power) corresponding to 0.5v on pin dim. current sensing during dimming, the current sensing circuitry (figure 15) detects over-current which can occur during hard-switching (see fault section), and zero-crossing to measure the phase of the total load current. to reject any switching noise which can occur at the turn-on of the low-side mosfet or igbt, a digital current sense blanking circuit blanks out the signal from the zero-crossing detection comparator for 400ns after lo goes 'high' (figure 16). 11 12 com lo 10 cs 1.6v q2 rcs 16 ho q2 15 vs half bridge output i load v bus (+) v bus (-) load return half bridge driver ir2159 phase control fault logic 400ns blank r1 figure 15, current sensing circuitry. the internal blank time reduces the dimming range slightly (figure 16) when operating at minimum phase shift (maximum lamp power). the external programming resistor on pin max must be selected such that the minimum phase shift is set a safe margin away from the blank time. a series resistor (r1) is required to limit the amount of current flowing out of pin cs when the voltage across rcs goes below -0.7v. a filter capacitor at pin cs may be required due to other possible asynchronous noise sources present in the ballast system.
ir21592/ir21593 ( s ) & ( pbf ) www.irf.com 21 ? blank v cs t lo switching noise dimming range fault mode (fault) during dimming, the peak current regulation circuit active during preheat and ignition is disabled. should non-zero voltage switching at the output of the half-bridge occur (figure 17), high current spikes will result. a lamp filament failure, lamp end-of-life, lamp removal, or a deadtime shorter than what is required for commutation, can all cause hard-switching. t t vs ho lo v cs 1.6v normal operation hard switching fault load removal figure 17, hard-switching with latch off figure 16, current sense timing diagram. should the peak voltage on pin cs exceed 1.6v at any time during dimming, the ir21592/ir21593 enters fault mode and the high and low-side driver outputs, ho and lo, are both turned off. cycling the supply voltage on vcc below uvlo- or the voltage on pin sd above and below sd+ and sd- will reset the ir21592/ir21593 to preheat (ph) mode (see state diagram). ballast design lamp requirements before selecting component values for the ballast output stage and the programmable inputs of the ir21592/ir21593, the following lamp requirements must first be defined: variable description units ph i filament pre-heat current arms ph t filament pre-heat time s max ph v maximum lamp pre-heat voltage vpp ign v lamp ignition voltage vpp % 100 p lamp power at 100% brightness w % 100 v lamp voltage at 100% brightness vpp % 1 p lamp power at 1% brightness w % 1 v lamp voltage at 1% brightness vpp min cath i minimum cathode heating current arms table i, typical lamp requirements
ir21592/ir21593 ( s ) & ( pbf ) 22 www.irf.com the operating frequency [hz] at maximum lamp power is given as: the cathode heating current at minimum lamp power is given as: 2 % 1 % 1 % 1 c f v i cath = (7) design constraints the inductor and capacitor values should be iterated until the following design constraints have been fulfilled (table ii). design constraint reason vv ph ph < max ignition during pre- heat ff khz ph ign ?> 5 production tolerances ii ign ign < max inductor saturation min % 1 cath cath i i lamp extinguishing during dimming table ii, ballast design constraints ir21592/ir21593 programmable inputs in order to program the min and max settings of the dimming interface, the phase of the output stage current at minimum and maximum lamp power must be calculated. this is obtained using the following equations: 2 2 2 % 100 2 4 % 100 2 2 % 100 4 % 100 2 2 % 100 % 100 4 1 32 1 32 1 2 1 c l v v v c p lc v c p lc f dc ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? = (6) ballast output stage the components comprising the output stage are selected using a set of equations. different ballast operating frequencies and their respective voltages and currents are calculated. the inductor and capacitor values are obtained using equations (2) through (7). the results of these equations reveal the location of each operating frequency and the corresponding voltages and currents. for a given l, c, dc bus voltage, and pre-heat current, the resulting voltage over the lamp during pre-heat is given as: the resulting operating frequency during pre-heat is given as: ph ph ph cv i f 2 = [hz] (3) the resulting operating frequency during ignition is given as: lc v v f ign dc ign 4 1 2 1 + = [hz] (4) the total load current during ignition is given as: ifcv ign ign ign = 2 [app] (5) dc ph dc ph v i c l v v 2 8 2 2 1 2 2 ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = (2)
ir21592/ir21593 ( s ) & ( pbf ) www.irf.com 23 ] 4 2 ) 2 2 [( tan 180 3 % 3 2 % 2 % % 2 % % % 2 % 1 % f lc p v f l v p c p v ? ? ? = ? (9) with the lamp requirements defined, the l and c of the ballast output stage selected, and the minimum and maximum phase calculated, the component values for setting the programmable inputs of the ir21592/ir21593 are obtained with the following equations: ) 14 2 ( ) 10000 ( ) 10 1 ( ) 10000 ( ) 6 25 ( ? ? ? ? ? ? ? ? = e f e f e r min min fmin [ohms] (10) ign cs i r ) 6 . 1 ( 2 ? = [ohms] (11) 2 ph cs fmin iph i r r r = [ohms] (12) ? ? ? ? ? ? ? = 45 1 4 % 1 ? fmin min r r [ohms] (14) [ohms] (15) ? ? ? ? ? ? ? ? ? ? ? ? = 45 1 4 86 . 0 % 100 ? fmin min min fmin max r r r r r 2 2 2 % 2 4 % 2 2 % 4 % 2 2 % % 4 1 32 1 32 1 2 1 c l v v v c p lc v c p lc f dc ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? = (8) ) )( 7 6 . 2 ( ph cph t e c ? = [farads] (13)
ir21592/ir21593 ( s ) & ( pbf ) 24 www.irf.com this ballast design procedure has been summarized into the following 3 steps: define lamp requirements iterate l and c to fulfill constraints calculate ir2159 programmable inputs figure 19, simplified ballast design procedure ir21592/ir21593
ir21592/ir21593 ( s ) & ( pbf ) www.irf.com 25 case outline 16 lead pdip 01-6015 01-3065 00 (ms-001a) 16 -lead soic (narrow body) 01-6018 01-3064 00 (ms-012ac)
ir21592/ir21593 ( s ) & ( pbf ) 26 www.irf.com ir world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 data and specifications subject to change without notice. this product has been designed and qualfied for the industrial market. 9/7/2005 lead free released non-lead free released part number date code irxxxxxx yww? ?xxxx pin 1 identifier ir logo lot code (prod mode - 4 digit spn code) assembly site code p ? marking code leadfree part marking information order information basic part (non-lead free) 16-lead pdip ir21592 order ir21592 16-lead soic ir21592s order ir21592s 16-lead pdip ir21593 order ir21593 16-lead soic ir21593s order ir21593s leadfree part 16-lead pdip ir21592 order ir21592pbf 16-lead soic ir21592s order ir21592spbf 16-lead pdip ir21593 order IR21593PBF 16-lead soic ir21593s order ir21593spbf

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